`timescale 1 ns / 100 ps

module Mux2To1_4_tb;

	reg sel;
	reg [3:0] a;
	reg [3:0] b;
	wire [3:0] out;

	Mux2To1_4 dut(sel, a, b, out);

	initial begin

		a = 4'b1010;
		b = 4'b0000;

		sel = 0; #10;
		sel = 1; #10;

		$stop;
	end

endmodule
